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HD74HC668, HD74HC669
Synchronous UP/Down Decade Counter Synchronous Up/Down 4-bit binary Counter
REJ03D0638-0200 (Previous ADE-205-520) Rev.2.00 Mar 30, 2006
Description
This synchronous presettable decade counter features an internal carry look-ahead for cascading in high-speed counting applications. Synchronous operation is provided by having all flip-flops clocked simultaneously so that the outputs change coincident with each other when so instructed by the count-enable inputs and internal gating. This mode of operation helps eliminate the output counting spikes that are normally associated with asynchronous (ripple-clock) counters. A buffered clock input triggers the four master-slave flip-flops on the rising (positive going) edge of the clock waveform. This counter is fully programmable; that is, the outputs may each be preset to either level. The load input circuitry allows loading with the carry-enable output of cascaded counters. As loading is synchronous, setting up a low level at the load input disables the counter and causes the outputs to agree with the data inputs after the next clock pulse. The carry look-ahead circuitry provides for cascading counters for n-bit synchronous applications without additional gating. Instrumental in accomplishing this function are two count enable inputs and a carry output. Both count enable inputs (P and T) must be low to count. The direction of the count is determined by the level of the up/down input. when the input is high, the counter counts up; when low, it counts down. Input T is fed forward to enable the carry output. The carry output thus enabled will produce a low-level output pulse with a duration approximately equal to the high portion of the QA output when counting up and approximately equal to the low portion of the QA output when counting down. This low level overflow carry pulse can be used to enable successive cascaded stages. Transitions at the enable P or T inputs are allowed regardless of the level of the clock input. All inputs are diode-clamped to minimize transission-line effects, thereby simplifying system design. This counter features a fully independent clock circuit. Changes at control inputs (enable P, Enable T, load, up/down) that will modify the operating mode have no effect until clocking occurs. The function of the counter (whether enabled, disabled, loading, or counting) will be dictated solely by the conditions meeting the stable setup and hold times.
Features
* High Speed Operation * High Output Current: Fanout of 10 LSTTL Loads * Wide Operating Voltage: VCC = 2 to 6 V * Low Input Current: 1 A max * Low Quiescent Supply Current: ICC (static) = 4 A max (Ta = 25C) * Ordering Information
Part Name HD74HC669P HD74HC669FPEL Package Type DILP-16 pin SOP-16 pin (JEITA) Package Code (Previous Code) PRDP0016AE-B (DP-16FV) PRSP0016DH-B (FP-16DAV) Package Abbreviation P FP -- EL (2,000 pcs/reel) EL (1,000 pcs/reel) Taping Abbreviation (Quantity)
HD74HC668RPEL PRSP0016DG-A RP SOP-16 pin (JEDEC) (FP-16DNV) HD74HC669RPEL Note: Please consult the sales office for the above package availability.
Rev.2.00 Mar 30, 2006 page 1 of 10
HD74HC668, HD74HC669
Pin Arrangement
HD74HC668
U/D CK A B C D Enable P GND
1 2 3 4 5 6 7 8
16 15 14 13 12 11 10 9
VCC
Ripple carry output
QA QB Outputs QC QD Enable T Load
Data inputs
(Top view)
HD74HC669
U/D CK A B C D Enable P GND
1 2 3 4 5 6 7 8
16 15 14 13 12 11 10 9
VCC
Ripple carry output
QA QB Outputs QC QD Enable T Load
Data inputs
(Top view)
Rev.2.00 Mar 30, 2006 page 2 of 10
HD74HC668, HD74HC669
Logic Diagram
HD74HC668
T
L Q Q
QA
U/D
IN
CK
DA Load Enable P Enable T DB
T IN L Q Q
QB
CK
T IN
L Q Q
QC
CK
DC
VCC
T IN L Q Q
QD
CK
DD RCO
CK
HD74HC669
T
Q Q
QA
U/D
IN
DA Load Enable P Enable T DB
T IN Q Q
QB
T IN
Q Q
QC
DC
T IN Q Q
QD
DD RCO
VCC
CK
Rev.2.00 Mar 30, 2006 page 3 of 10
HD74HC668, HD74HC669
Timing Chart
HD74HC668
Load A B Data inputs C D
Clock U/D Enable P and T QA QB QC QD
Ripple carry output
7
8
9
0
1
2
2
2
1
0
9
8
7
Count up Load
Inhibit
Count down
Rev.2.00 Mar 30, 2006 page 4 of 10
HD74HC668, HD74HC669 HD74HC669
Load A B Data inputs C D
Clock
U/D P and T
QA
QB
QC
QD
Ripple carry output 13 14 15 0 1 2 2 2 1 0 15 14 13
Count up Load
Inhibit
Count down
Absolute Maximum Ratings
Item Supply voltage range Input / Output voltage Input / Output diode current Output current VCC, GND current Power dissipation Storage temperature Symbol VCC VIN, VOUT IIK, IOK IO ICC or IGND PT Tstg Ratings -0.5 to 7.0 -0.5 to VCC +0.5 20 25 50 500 -65 to +150 Unit V V mA mA mA mW C
Note: The absolute maximum ratings are values, which must not individually be exceeded, and furthermore, no two of which may be realized at the same time.
Rev.2.00 Mar 30, 2006 page 5 of 10
HD74HC668, HD74HC669
Recommended Operating Conditions
Item Supply voltage Input / Output voltage Operating temperature Input rise / fall time Note:
*1
Symbol VCC VIN, VOUT Ta tr , tf
Ratings 2 to 6 0 to VCC -40 to 85 0 to 1000 0 to 500 0 to 400
Unit V V C
Conditions
VCC = 2.0 V ns VCC = 4.5 V VCC = 6.0 V
1. This item guarantees maximum limit when one input switches. Waveform: Refer to test circuit of switching characteristics.
Electrical Characteristics
Ta = 25C Item Input voltage Symbol VCC (V) VIH 2.0 4.5 6.0 VIL 2.0 4.5 6.0 2.0 4.5 6.0 4.5 6.0 VOL 2.0 4.5 6.0 4.5 Input current Quiescent supply current Iin ICC 6.0 6.0 6.0 Min 1.5 3.15 4.2 -- -- -- 1.9 4.4 5.9 4.18 5.68 -- -- -- -- -- -- -- Typ -- -- -- -- -- -- 2.0 4.5 6.0 -- -- 0.0 0.0 0.0 -- -- -- -- Max -- -- -- 0.5 1.35 1.8 -- -- -- -- -- 0.1 0.1 0.1 0.26 0.26 0.1 4.0 Ta = -40 to+85C Min 1.5 3.15 4.2 -- -- -- 1.9 4.4 5.9 4.13 5.63 -- -- -- -- -- -- -- Max -- -- -- 0.5 1.35 1.8 -- -- -- -- -- 0.1 0.1 0.1 0.33 0.33 1.0 40 V IOH = -4 mA IOH = -5.2 mA Vin = VIH or VIL IOL = 20 A V Unit V Test Conditions
Output voltage
VOH
V
Vin = VIH or VIL IOH = -20 A
IOL = 4 mA IOL = 5.2 mA A Vin = VCC or GND A Vin = VCC or GND, Iout = 0 A
Rev.2.00 Mar 30, 2006 page 6 of 10
HD74HC668, HD74HC669
Switching Characteristics (CL = 50 pF, Input tr = tf = 6 ns)
Ta = 25C Item Maximum clock Frequency Propagation delay time Symbol VCC (V) fmax 2.0 4.5 6.0 tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL Pulse width tw 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 tsu 2.0 4.5 6.0 2.0 4.5 6.0 tsu 2.0 4.5 6.0 2.0 4.5 6.0 Output rise/fall time Input capacitance tTLH tTHL Cin 2.0 4.5 6.0 -- Min -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 80 16 14 100 20 17 150 30 26 150 30 26 150 30 26 5 5 5 -- -- -- -- Typ -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 5 -- 5 Max 5 27 32 200 40 34 225 45 38 150 30 26 200 40 34 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 75 15 13 10 Ta = -40 to +85C Min -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 100 20 17 125 25 21 190 38 33 190 38 33 190 38 33 5 5 5 -- -- -- -- Max 4 21 25 250 50 43 280 56 48 190 38 33 250 50 43 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 95 19 16 10 ns ns U/D to Clock ns Enable P, T to Clock ns ns Enable T to Ripple carry out ns Clock to Ripple carry out Unit MHz Test Conditions
ns
Clock to Q
ns
U/D to Ripple carry out
Setup time
tsu
ns
Data to Clock
tsu
ns
Loadk to Clock
Hold time
th
ns
pF
Rev.2.00 Mar 30, 2006 page 7 of 10
HD74HC668, HD74HC669
Test Circuit
VCC VCC Output U/D Input Clock QA Output QB Output QC Output QD Output CL = 50 pF CL = 50 pF Note : 1. CL includes probe and jig capacitance. CL = 50 pF CL = 50 pF CL = 50 pF
See Function Table
Pulse Generator Zout = 50 Input Pulse Generator Zout = 50
A B C D Enable P Load
Ripple Enable T Carry
Rev.2.00 Mar 30, 2006 page 8 of 10
HD74HC668, HD74HC669
Package Dimensions
JEITA Package Code P-DIP16-6.3x19.2-2.54 RENESAS Code PRDP0016AE-B Previous Code DP-16FV MASS[Typ.] 1.05g
D
16
9
1 0.89 b3
8
Z
A1
A
E
Reference Symbol
Dimension in Millimeters
Min
e
bp
e1
c
( Ni/Pd/Au plating )
e1 D E A A1 bp b3 c e Z L
Nom Max 7.62 19.2 20.32 6.3 7.4 5.06
L
0.51 0.40 0.48 0.56 1.30 0.19 0.25 0.31 0 15 2.29 2.54 2.79 1.12 2.54
JEITA Package Code P-SOP16-5.5x10.06-1.27
RENESAS Code PRSP0016DH-B
Previous Code FP-16DAV
MASS[Typ.] 0.24g
*1
D F 9
16
NOTE) 1. DIMENSIONS"*1 (Nom)"AND"*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET.
bp
HE
E
Index mark
*2
Terminal cross section ( Ni/Pd/Au plating )
1 Z e
*3
8 bp x M L1
Reference Symbol
c
Dimension in Millimeters
A1
y
L
Detail F
D E A2 A1 A bp b1 c c1 HE e x y Z L L1
Min Nom Max 10.06 10.5 5.50 0.00 0.10 0.20 2.20 0.34 0.40 0.46 0.15 0.20 0.25 0 8 7.50 7.80 8.00 1.27 0.12 0.15 0.80 0.50 0.70 0.90 1.15
Rev.2.00 Mar 30, 2006 page 9 of 10
A
HD74HC668, HD74HC669
JEITA Package Code P-SOP16-3.95x9.9-1.27 RENESAS Code PRSP0016DG-A Previous Code FP-16DNV MASS[Typ.] 0.15g
*1
D 9
F
16
NOTE) 1. DIMENSIONS"*1 (Nom)"AND"*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET.
bp
E HE
Index mark
*2
Terminal cross section ( Ni/Pd/Au plating )
1 Z e
*3
c
8 bp x M L1
Reference Symbol
Dimension in Millimeters
A1
L
y
Detail F
D E A2 A1 A bp b1 c c1 HE e x y Z L L1
Min Nom Max 9.90 10.30 3.95 0.10 0.14 0.25 1.75 0.34 0.40 0.46 0.15 0.20 0.25 0 8 5.80 6.10 6.20 1.27 0.25 0.15 0.635 0.40 0.60 1.27 1.08
Rev.2.00 Mar 30, 2006 page 10 of 10
A
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